RTOS embedded in the MSP430F148 microcontroller(4)
source: application Author: Li Qiang Zhang Junmo Chen Yao : 2010-09-12-
the so-called will interrupt stack and task stack in the memory isolation, is special open up a region as the interrupt stack, interrupt only use it for any one task run time. Design principles: one is to minimize the interruption of separate tasks and common tasks; two is the simulation of the interrupt stack pointer must always remain on top of the interrupt stack, the interrupt interrupt stack pointer to keep synchronous with the change of SP.
in order to achieve this goal, the chip must have the following 2 conditions.
first, the chip must have a general register and the corresponding instruction can imitate the stack pointer to the function of SP, which can realize the software stack. The following command simulation function of SP in MSP430 Series MCU (R4 as interrupt stack pointer):
MOV @R4+, SP; R4 to address the contents into the SP, while R4 content; 2
MOV SP, 0 (R4); the SP content in the R4 to address
MOV @R4+, PC; R4 to address the contents into the PC, while R4 content; 2
secondly, as simulated interrupt register R4 the stack pointer to any situation, in addition to the unused interrupt. Because of this, the R4 must always remain on top of the interrupt stack, if change its value, will change the interrupt stack structure. Generally this is required by the compiler to guarantee, in which we use IAR compiler, there is an option to avoid the use of R4 and / or R5.
the specific design, we each task in uC/OS-II TCB (task control block) to join the following structure:
TSP-- task stack pointer. After the interruption, pointing to the task at the top of the stack.
ISP-- interrupt stack pointer. If the task switching in the interruption, the top point to the task in the interrupt stack the saved state.
FromInt logo -- whether from interrupt flag. Used to determine the task state is stored in the interrupt stack (1), or stored in the task stack (0).
below assume a common task 1 in executive process interruption, analyze it in the interrupt the execution of several situations that may occur during the process of.
(1) caused the interrupt in ordinary task 1 is running, no activation of higher priority tasks in the interruption, but normal interrupt, continue to perform the task of 1, as shown in figure 2.
began to interrupt: will be saved in the current task stack SR and PC moved to the interrupt stack is stored in the interrupt occurs, while the SP back to before the interruption position and save it to the task of TCB TSP (which is to the end of interrupt, the task of maintaining the continuity of stack), and then SP refers to the top of the interrupt stack, according to the custom of stack structure in order to all registers are saved to the interrupt stack. Save the process R4 must keep synchronous change and SP, while the FromInt flag is set to L.
Exit interrupt: because of the higher priority task is not active, so the interrupting task is completed, will be the normal order of exit interrupt, will save roll stack on the interrupt stack registers, the FromInt flag is set to 0, SP to the task stack, finally, PC pointer to the return address before the interruption, continue to run.
(2) caused the interrupt in ordinary task 1 is running, in the interrupt is activated in a higher priority task 2. End of interrupt by the task scheduler scheduling to enforce higher priority task 2, did not return to normal task 1.
when performing a task 2, task scheduler will task 2 preserved in their task stack state recovery and perform the task 2. After the implementation, if no activation of higher priority tasks, then according to the priority principle, scheduler will schedule execution task 1. Through the judgment task 1 TCB FromInt logo, can know the task 1 state is stored in the task stack and interrupt stack, which can be in the state of recovery, continue to run.
(3) caused the interrupt in ordinary task 1 is running, in the interrupt activation of higher priority tasks 2, 2 missions and interruption.
because uC/OS-II is strictly for task scheduling according to priority preemptive principle, so the task state is saved in the interrupt stack top priorities than state is saved beneath it in the task of high priority. At execution time, is performed by a top to bottom interrupt stack sequence. In this hypothesis, we must first perform the task of 2, and then perform the task of 1, as shown in figure 3.
4) that caused the interrupt in the ordinary task 1 is running, in the interrupt activation of higher priority task 2. In the execution of task 2 and task interruption, interruption in the process of 2 due to waiting for the signal has been suspended.
it has been banned in the system the initial design, uses the signal quantity will interrupt pending is not allowed in the interruption.
(5) caused the interrupt in ordinary task 1 is running, in the interrupt is activated in a higher priority task 2. In the execution of task 2 and interrupt, interrupt is enabled in the higher priority task 3. End of interrupt by the task scheduler scheduling to enforce higher priority task 3.
this situation and discuss the situation is the same as the 2.
(6) high priority task 2 is a higher priority task 3 aborted, in task 3 run after, task scheduler will direct execution task 1 (according to the priority scheduling).
because each task of ISP and TSP in the task before switching have been preserved in the TCB of tasks, task 1 stack pointer and R4 can go back to the task in the task stack and interrupt stack in the correct position.
Task 2 aborted includes two kinds of situations. One is the task 2 is another task to delete this task, 2 in the interrupt stack space will automatically release. Two is the task 2 is another task to hang, at this time should be in the program hangs the function TaskSuspend () to add a section of code, save it in the interrupt stack state transition to their task stack, at the same time, the TCB FromInt flag is set to 0. So, in task 2 release hanging up, go to the state recovery task stack.
(7) interrupt nesting interrupt occurs in.
occurrence of interrupt nesting, should be treated according to the mechanism of interrupt nesting. First of all, in the interrupt nesting, task scheduling, not allowed to do so, even in the interrupt nesting inspired a higher priority task, must wait until the last interrupt before scheduling execution before exit. This is guaranteed by the design of uC/OS-II system. Secondly, RAM byte register and function call occupied all the interrupt nesting. In the exit interrupt nesting, not bound to TCB FromInt reset.
